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SUMMARY:KEYNOTE 7: Coreless Continuum Computer Architecture
DTSTART;VALUE=DATE-TIME:20181205T160000Z
DTEND;VALUE=DATE-TIME:20181205T164500Z
DTSTAMP;VALUE=DATE-TIME:20260814T182700Z
UID:indico-contribution-163-670@events.chpc.ac.za
DESCRIPTION:Speakers: Thomas Sterling (Indiana University)\n**Coreless Con
 tinuum Computer Architecture**\n\n> *Thomas Sterling* (Department of Intel
 ligent Systems Engineering\, School of Informatics\, Computing\, and Engin
 eering\, Indiana University)\n\n\n\n\nAs introduced at CHPC-17\, a new era
  is dawning: the Neo-Digital Age as semiconductor fabrication enters its f
 inal phase with nano-scale feature size. For the first time in three decad
 es\, fundamental technology limitations of device density\, power consumpt
 ion\, clock rate\, and instruction level parallelism are demanding revolut
 ionary practices to further expand HPC capabilities into the trans-exascal
 e performance regime and perhaps beyond. Among the domains of possible cha
 nge are those uncovered in the prevailing assumptions embodied by the many
  generations exploiting Moore’s Law\, which no longer apply. These inclu
 de 1) the use of static methods for parallel application programming and s
 tatic resource management\, and 2) the implicit underlying principles buri
 ed in the von Neumann architecture of which essentially all HPC systems ar
 e since derivatives. An alternative strategy\, bordering on a paradigm shi
 ft\, reverses conventional methodologies a) to employ dynamic adaptive met
 hods of resource management and task scheduling\, and b) to eliminate von 
 Neumann bottlenecks\, eliminating even the basic core that has endured as 
 the foundation of HPC architecture design since the late 1940s. Central to
  the forward looking revolution is the elimination of the FPU/ALU as the p
 recious resource with the implied objective function of highest possible u
 tilization. The Continuum Computer Architecture (CCA) has been proposed as
  a family of alternative architectures that address the current challenge 
 and exploit the future opportunities by fully integration of logic\, memor
 y\, control\, and communication within a single highly replicated computin
 g cell. First suggested an abstract in last year’s last Keynote\, this p
 resentation will expose key details in structure and semantics that will l
 ayout the conceptual scaffolding for future development and application su
 ch as machine learning and intelligence\, planning\, scheduling\, hypothes
 is testing\, facial recognition and many other graph-based application. Qu
 estions will be encouraged by participants throughout the presentation as 
 well as the Q&A session at the end.\n\nhttps://events.chpc.ac.za/event/33/
 contributions/670/
LOCATION: Hall B+C
URL:https://events.chpc.ac.za/event/33/contributions/670/
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