BEGIN:VCALENDAR VERSION:2.0 PRODID:-//CERN//INDICO//EN BEGIN:VEVENT SUMMARY:Trends and challenges in HPC from Dell Technologies DTSTART;VALUE=DATE-TIME:20211202T101500Z DTEND;VALUE=DATE-TIME:20211202T104500Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1615@events.chpc.ac.za DESCRIPTION:Speakers: Kris Buggenhout ()\nThe talk will cover some of the trends in power\, cpu tech\, and the challenges we are being faced by our technology partners pushing the limits.\n\nhttps://events.chpc.ac.za/event /98/contributions/1615/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1615/ END:VEVENT BEGIN:VEVENT SUMMARY:Update on High Performance Computing at HPE DTSTART;VALUE=DATE-TIME:20211202T093000Z DTEND;VALUE=DATE-TIME:20211202T100000Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1599@events.chpc.ac.za DESCRIPTION:Speakers: Duncan Roweth ()\nThis talk will provide an update o n the way HPE is working with customers to provide technology and solution s to address the most challenging problems in high performance computing. It will include the need to make use of heterogeneous computing elements\, and how AI can be combined with HPC to enable end users to be more produc tive\n\nhttps://events.chpc.ac.za/event/98/contributions/1599/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1599/ END:VEVENT BEGIN:VEVENT SUMMARY:Online Education: Surprises and Insights DTSTART;VALUE=DATE-TIME:20211203T131500Z DTEND;VALUE=DATE-TIME:20211203T141500Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1584@events.chpc.ac.za DESCRIPTION:Speakers: Bryan Johnston (CHPC)\, Verena Ras (University of Ca pe Town \; H3ABioNet)\n**BoF: Online Education: Surprises and Insights** \ n\n\nFor some\, the move to online education and training took place many years ago\, while for others\, the need to move online was thrust upon the m due to the global pandemic. No matter what the circumstances or motivati ons for the move\, the community of online educators and trainers have all encountered challenges\, experienced surprises\, and gained insights from their journeys into the online education space. After migrating\, some ha ve met with varying levels of success\, while others still struggle to est ablish a reliable and effective online programme. \n\nThis panel session w ill discuss some of the challenges in moving to an online education platfo rm. We will hear personal experiences from established online trainers fro m various regions about how they have implemented their programmes\, what surprises they experienced along the way\, and what insights they can shar e with others trying to move to an online education model. \n\nSpeakers: \ n\n - **David Joyner** (Georgia Tech)\; \n - **Ben Morse** (EPCC)\; \n - **Verena Ras** (CBIO)\n\nModerator: \n\n - **Bryan Johnston** (CHPC)\n\nh ttps://events.chpc.ac.za/event/98/contributions/1584/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1584/ END:VEVENT BEGIN:VEVENT SUMMARY:HPC Cloud Use Cases and Best Practices DTSTART;VALUE=DATE-TIME:20211202T104500Z DTEND;VALUE=DATE-TIME:20211202T111500Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1576@events.chpc.ac.za DESCRIPTION:Speakers: Fritz Ferstl (Altair)\nThis talk will discuss the cu rrent state-of-the-art of HPC cloud usage in various application sectors a nd will look at best practices and common pitfalls when adopting cloud inf rastructures for HPC. The focus will be on non-trivial use cases. Concrete examples of existing cloud deployments will showcase what is feasible and advisable today. The talk will also give a perspective on trends and futu re developments.\n\nhttps://events.chpc.ac.za/event/98/contributions/1576/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1576/ END:VEVENT BEGIN:VEVENT SUMMARY:Leveraging New Interfaces to Low-Latency Storage DTSTART;VALUE=DATE-TIME:20211202T134500Z DTEND;VALUE=DATE-TIME:20211202T141500Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1486@events.chpc.ac.za DESCRIPTION:Speakers: Luke Logan (Illinois Institute of Technology)\nThe g ap between I/O performance and memory performance is decreasing due to the emergence of fast\, low-latency storage such as NVMe and persistent memor y (PMEM). However\, traditional interfaces to storage (e.g.\, POSIX) do no t fully leverage these new device characteristics\, resulting in significa nt performance degradation. New interfaces to storage must be utilized in order to achieve the full potential of these low-latency technologies. To demonstrate this\, we present pMEMCPY: a simple\, lightweight\, and portab le I/O library for storing data in persistent memory. As opposed to tradit ional storage APIs\, pMEMCPY uses memory mapping. We demonstrate that our approach is up to 2x faster than alternative interfaces to storage under r eal workloads.\n\nhttps://events.chpc.ac.za/event/98/contributions/1486/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1486/ END:VEVENT BEGIN:VEVENT SUMMARY:SCTuner— an autotuner for I/O library DTSTART;VALUE=DATE-TIME:20211202T131500Z DTEND;VALUE=DATE-TIME:20211202T134500Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1488@events.chpc.ac.za DESCRIPTION:Speakers: Bing Xie (ORNL)\nIn HPC\, typical scientific codes often manage a massive amount of data utilizing I/O middle ware libraries\, such as HDF5\, PnetCDF\, ADIOS\, etc. These libraries support a variety of data structures and allow end users to optimize I/O p erformance by tuning configurations across multiple layers of the HPC I/O middleware stack. This work proposes SCTuner\, an autotuner built within t he I/O library itself to tune the configurations across I/O layers dynamic ally and agilely at application runtime. To this end\, we introduce an I/O statistical benchmarking method to profile the behaviors of individ ual supercomputer I/O subsystems with varied configurations across I/O lay ers. Next\, we use the benchmarking results as the built-in knowledge in S CTuner\, implement an I/O pattern extractor\, and plan to implement an on line performance tuner as the runtime of SCTuner. We conducted a benchmark ing analysis on the Summit supercomputer and its GPFS file system Alpine. The preliminary results show that our method can effectively extract the c onsistent I/O behaviors of the target system under production load\, building the base for I/O autotuning at application runt ime.\n\nhttps://events.chpc.ac.za/event/98/contributions/1488/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1488/ END:VEVENT BEGIN:VEVENT SUMMARY:Evaluating and Characterizing Parallel I/O in HPC Systems: Best Pr actices and Future Directions DTSTART;VALUE=DATE-TIME:20211202T123000Z DTEND;VALUE=DATE-TIME:20211202T130000Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1484@events.chpc.ac.za DESCRIPTION:Speakers: Sarah Neuwirth (Goethe-University Frankfurt)\nAs a recent I/O behaviour analysis [1] has revealed\, High Performance C omputing(HPC) storage systems may no longer be dominated by write I/O – challenging the long- and widely-held belief that HPC workloads are write-intensive. HPC applications are evolving to include not only tradit ional scale-up modelling and simulation bulk-synchronous workloads but als o scale-out workloads [2] like artificial intelligence (AI)\,advanc ed and big data analytics [3]\, machine learning\, deep learning [4]\, and complex multi-step workflows [5]–[7]. Exascale workflow s are projected to include multiple different components from both scale-up and scale-out communities operating together to drive scient ific discovery and innovation.With the often conflicting design choices be tween optimizing for write-intensive vs. read-intensive workloads\, having flexible I/O systems will be crucial to support these emer ging hybrid workloads. Another performance aspect is the intensifyi ng complexity of parallel file and storage systems in large-scale cluster environments. Storage system designs are advancing beyond the traditional two-tiered file system and archive model by introd ucing new tiers of temporary\,fast storage close to the computing resources with distinctly different performance characteristics. The c hanging landscape of emerging hybrid HPC workloads along with the ever increasing gap between the compute and storage performance cap abilities reinforce the need for an in-depth understanding of extre me-scale parallel I/O and for rethinking existing data storage and managem ent evaluation techniques and strategies.In this talk\, an overview a nd taxonomy [8] of the current state-of-the-art research on large-sca le parallel I/O evaluation and characterization techniques in the context of HPC systems is presented. Traditionally\, the process of understanding large-scale I/O behaviour and performance for specific applications or storage systems is performed iteratively and empirically in a closed l oop fashion\, as outlined in Figure 1\, and consists of three main phases: (1) Measurements and Statistics Collection\, (2) Modelling and Prediction \, and (3) Simulation. The overview and broad knowledge base provided by t his talk is invaluable to the whole scientific community\, as applications often observe poor performance due to bottlenecks in the parallel I/O and storage system. In addition\, this talk aims to identify future re-search challenges with regard to emerging exascale computing systems an d more complex hybrid HPC workloads.\n\nhttps://events.chpc.ac.za/event/98 /contributions/1484/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1484/ END:VEVENT BEGIN:VEVENT SUMMARY:Virtual Log-Structured Storage for High-Performance Streaming DTSTART;VALUE=DATE-TIME:20211202T120000Z DTEND;VALUE=DATE-TIME:20211202T123000Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1478@events.chpc.ac.za DESCRIPTION:Speakers: Ovidiu-Cristian Marcu (University of Luxembourg)\nOv er the past decade\, given the higher number of data sources (e.g.\, Cloud applications\, Internet of things) and critical business demands\, Big Da ta transitioned from batch-oriented to real-time analytics. Stream storage systems\, such as Apache Kafka\, are well known for their increasing role in real-time Big Data analytics. For scalable stream data ingestion and p rocessing\, they logically split a data stream topic into multiple partiti ons. Stream storage systems keep multiple data stream copies to protect ag ainst data loss while implementing a stream partition as a replicated log. This architectural choice enables simplified development while trading cl uster size with performance and the number of streams optimally managed. T his paper introduces a shared virtual log-structured storage approach for improving the cluster throughput when multiple producers and consumers wri te and consume in parallel data streams. Stream partitions are associated with shared replicated virtual logs transparently to the user\, effectivel y separating the implementation of stream partitioning (and data ordering) from data replication (and durability). We implement the virtual log tech nique in the KerA stream storage system. When comparing with Apache Kafka\ , KerA improves the cluster ingestion throughput (for replication factor t hree) by up to 4x when multiple producers write over hundreds of data stre ams. Furthermore\, we present the initial results of running experiments w ith KerA over Infiniband and Singularity in an HPC cluster.\n\nhttps://eve nts.chpc.ac.za/event/98/contributions/1478/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1478/ END:VEVENT BEGIN:VEVENT SUMMARY:BoF: NVIDIA Deep Learning Institute – bringing AI and GPU-accel erated computing to Academic Institutions DTSTART;VALUE=DATE-TIME:20211203T120000Z DTEND;VALUE=DATE-TIME:20211203T130000Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1571@events.chpc.ac.za DESCRIPTION:Speakers: Kevin McFall (NVIDIA)\nBirds-of-a-Feather (BoF)\n\nT he NVIDIA Deep Learning Institute (DLI) offers resources for diverse learn ing needs giving individuals\, teams\, organizations\, educators\, and stu dents what they need to advance their knowledge in accelerated computing\, AI\, accelerated data science\, graphics and simulation\, and more. Many DLI programs specifically target academia with the goal of providing facul ty with free training for themselves and their students. This includes fac ulty development workshops\, a certification program for faculty to delive r NVIDIA training material on NVIDIA hardware\, and teaching kits with wor ked problems\, access to online training\, and credits for cloud GPU resou rces. Other NVIDIA programs for academia include a hardware grant program\ , graduate fellowships\, and other funding opportunities. This session wil l present the programs NVIDIA has to offer academia and how they can suppo rt both instruction and research.\n \nTarget Audience: instructional and r esearch faculty in accelerated computing\, AI\, and data science\n\nhttps: //events.chpc.ac.za/event/98/contributions/1571/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1571/ END:VEVENT BEGIN:VEVENT SUMMARY:Introducing Cloud-Native Supercomputing: Bare-Metal\, Secured Supe rcomputing Architecture DTSTART;VALUE=DATE-TIME:20211202T090000Z DTEND;VALUE=DATE-TIME:20211202T093000Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1527@events.chpc.ac.za DESCRIPTION:Speakers: Gilad Shainer (NVIDIA)\, David Slama ()\nHigh-perfor mance computing and artificial intelligence have driven supercomputers int o wide commercial use as the primary data processing engines enabling rese arch\, scientific discoveries\, and product development. Extracting the hi ghest possible performance from supercomputing systems while achieving eff icient utilization has traditionally been incompatible with the secured\, multi-tenant architecture of modern cloud computing. A cloud-native superc omputing platform aims at the goal of combining peak system performance wi th a modern zero-trust model for security isolation and multi-tenancy. The key element enabling this architecture transition is the data processing unit (DPU). \n\nThe DPU is a fully integrated data-center-on-a-chip platfo rm that imbues each supercomputing node with two new capabilities: First\, an infrastructure control plane\nprocessor that secures user access\, sto rage access\, networking\, and life-cycle orchestration for the computing node in the data center or at the edge\, offloading\nthese services from t he main compute processor and enabling bare-metal multi-\ntenancy. Second\ , an isolated line-rate data path with hardware acceleration that\nenables high performance. All this infrastructure allows a cloud-native HPC and\n AI platform architecture that delivers HPC performance on an infrastructur e\nplatform that meets cloud services requirements. The implementation of the infrastructure comes from the open-source community and driven by stan dards\, similarly as how some of the traditional HPC software stack that i s maintained by a community including commercial companies\, academic orga nizations\, and government agencies.\n\nWe'll introduce the new supercompu ting architecture\, discuss the first cloud native supercomputers\, \, rev iew first applications performance results\, and explore future directions .\n\nhttps://events.chpc.ac.za/event/98/contributions/1527/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1527/ END:VEVENT BEGIN:VEVENT SUMMARY:FPGA Acceleration of GWAS Permutation Testing DTSTART;VALUE=DATE-TIME:20211203T104500Z DTEND;VALUE=DATE-TIME:20211203T111500Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1529@events.chpc.ac.za DESCRIPTION:Speakers: Yaniv Swiel (Wits)\nThe large sample sizes of modern genetic datasets has necessitated the development of high-throughput acce lerators in order to allow bioinformatics research to be performed in a re asonable amount of time. Although the inherently parallel nature of FPGAs makes them well suited to accelerating high-throughput workloads\, they ar e not commonly employed as bioinformatics accelerators (in lieu of CPUs an d/or GPUs) due to their high cost and the fact that developing FPGA-accele rated algorithms is a more complex and time-consuming process than the dev elopment of software for CPUs or GPUs. The availability of cloud-based FPG A instances\, however\, has made powerful FPGAs accessible to bioinformati cs labs and the continuous improvement of FPGA design tools has reduced mu ch of the complexity of FPGA development.\n\nThis work determines the effi cacy of FPGAs when applied to the acceleration of GWAS permutation testing - a computationally expensive bioinformatics algorithm that involves the repeated multiplication of a constant matrix with a changing vector - by p resenting the design and evaluation of an FPGA-based accelerator designed to run on an AWS EC2 FPGA instance. \n\nThis work shows that the FPGA acce lerator is orders of magnitude faster than a popular CPU-based GWAS tool w ithout an apparent loss of accuracy. Furthermore\, this work demonstrates that FPGA acceleration enables the handling of workloads which are almost unfeasible for current CPU-based methods. This work\, therefore\, proves t hat FPGAs can effectively accelerate high-throughput bioinformatics worklo ads at relatively low cost.\n\nhttps://events.chpc.ac.za/event/98/contribu tions/1529/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1529/ END:VEVENT BEGIN:VEVENT SUMMARY:Prime Number algorithm for massively parallel Processor-in-memory machine DTSTART;VALUE=DATE-TIME:20211203T101500Z DTEND;VALUE=DATE-TIME:20211203T104500Z DTSTAMP;VALUE=DATE-TIME:20260608T113533Z UID:indico-contribution-537-1528@events.chpc.ac.za DESCRIPTION:Speakers: Andy Rabagliati (UCT)\nPrime Number algorithm for ma ssively parallel Processor-in-memory machine\n\nDoing Sieve of Eratosthene s on a 1024-way bit-serial processor implemented on an FPGA\n\nThe bit-ser ial processors very simple\, backed with 512 bits of RAM.\n\nAll processor s perform the same operation\, subject to individual processor\nenables\, encompassing boolean logic\, and can read and write their own\n512 bit RAM .\n\nThe 512 bits are allocated among variables\, of arbitrary width\, per haps 32 bits.\n\nBy a succession of boolean operations\, addition\, subtra ction multiply and\ndivide are coded into routines. All these operations h appen in parallel.\n\nAlgorithm design can be difficult\, as all program b ranch paths must be traversed.\n\nA simple sieve on a regular processor ta kes time proportional to the total\nnumber of candidate primes tested\, an d the number of factors used in the divisions.\n\nI present a sieve algori thm with time only proportional to the number of factors.\n\nhttps://event s.chpc.ac.za/event/98/contributions/1528/ LOCATION: URL:https://events.chpc.ac.za/event/98/contributions/1528/ END:VEVENT END:VCALENDAR