3-7 December 2017
Velmoré Hotel Estate
Africa/Johannesburg timezone

Accelerating the 3-D FFT using a heterogeneous FPGA architecture

5 Dec 2017, 11:00
25m
Tres Sage (Velmoré Hotel Estate)

Tres Sage

Velmoré Hotel Estate

96 Main Road (M26) Hennops River Erasmia
Talk HPC Techniques and Computer Science HPC

Speaker

Matthew Anderson (Indiana University)

Description

Future Exascale architectures will likely make extensive use of computing accelerators such as Field Programmable Gate Arrays (FPGAs) given that these accelerators are very power efficient. Oftentimes, these FPGAs are located at the network interface card (NIC) and switch level in order to accelerate network operations, incorporate contention avoiding routing schemes, and perform computations directly on the NIC and bypass the arithmetic logic unit (ALU) of the CPU. This talk explores just such a heterogeneous FPGA architecture in the context of two kernels that are driving applications in leadership machines: the 3- D Fast Fourier Transform (3-D FFT) and Asynchronous Multi-Tasking (AMT). The machine explored here is a DataVortex system which consists of conventional processors but with programmable logic incorporated in the memory architecture. The programmable logic controls the network and is incorporated both in the network interface cards and the network switches and implements a contention avoiding network routing. Both the 3-D FFT and AMT kernels show compelling performance for deployment to FFT driven applications in both molecular dynamics and density functional theory.

HPC content

Future Exascale architectures will likely make extensive use of computing accelerators such as Field Programmable Gate Arrays (FPGAs) given that these accelerators are very power efficient. Oftentimes, these FPGAs are located at the network interface card (NIC) and switch level in order to accelerate network operations, incorporate contention avoiding routing schemes, and perform computations directly on the NIC and bypass the arithmetic logic unit (ALU) of the CPU. This talk explores just such a heterogeneous FPGA architecture in the context of several kernels that are driving applications in leadership machines.

Primary author

Matthew Anderson (Indiana University)

Co-authors

Maciej Brodowicz (Indiana University) Martin Swany (Indiana University) Thomas Sterling (Indiana University)

Presentation Materials

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